Prizes versus Wages with Envy and Pride

We show that if agents are risk neutral, prizes outperform wages when there is sufficient pride and envy relative to the noisiness of performance. If agents are risk averse, prizes are a necessary supplement to wages (as bonuses).Envy, Pride, Wages, Prizes, Bonus

Exploiting Fine-Grain Concurrency Analytical Insights in Superscalar Processor Design

This dissertation develops analytical models to provide insight into various design issues associated with superscalar-type processors, i.e., the processors capable of executing multiple instructions per cycle. A survey of the existing machines and literature has been completed with a proposed classification of various approaches for exploiting fine-grain concurrency. Optimization of a single pipeline is discussed based on an analytical model. The model-predicted performance curves are found to be in close proximity to published results using simulation techniques. A model is also developed for comparing different branch strategies for single-pipeline processors in terms of their effectiveness in reducing branch delay. The additional instruction fetch traffic generated by certain branch strategies is also studied and is shown to be a useful criterion for choosing between equally well performing strategies. Next, processors with multiple pipelines are modelled to study the tradeoffs associated with deeper pipelines versus multiple pipelines. The model developed can reveal the cause of performance bottleneck: insufficient resources to exploit discovered parallelism, insufficient instruction stream parallelism, or insufficient scope of concurrency detection. The cost associated with speculative (i.e., beyond basic block) execution is examined via probability distributions that characterize the inherent parallelism in the instruction stream. The throughput prediction of the analytic model is shown, using a variety of benchmarks, to be close to the measured static throughput of the compiler output, under resource and scope constraints. Further experiments provide misprediction delay estimates for these benchmarks under scope constraints, assuming beyond-basic-block, out-of-order execution and run-time scheduling. These results were derived using traces generated by the Multiflow TRACE SCHEDULING™(*) compacting C and FORTRAN 77 compilers. A simplified extension to the model to include multiprocessors is also proposed. The extended model is used to analyze combined systems, such as superpipelined multiprocessors and superscalar multiprocessors, both with shared memory. It is shown that the number of pipelines (or processors) at which the maximum throughput is obtained is increasingly sensitive to the ratio of memory access time to network access delay, as memory access time increases. Further, as a function of inter-iteration dependency distance, optimum throughput is shown to vary nonlinearly, whereas the corresponding Optimum number of processors varies linearly. The predictions from the analytical model agree with published results based on simulations. (*)TRACE SCHEDULING is a trademark of Multiflow Computer, Inc

Efficient Rijndael Encryption Implementation with Composite Field Arithmetic

Abstract. We explore the use of subfield arithmetic for efficient imple-mentations of Galois Field arithmetic especially in the context of the Rijndael block cipher. Our technique involves mapping field elements to a composite field representation. We describe how to select a represen-tation which minimizes the computation cost of the relevant arithmetic, taking into account the cost of the mapping as well. Our method results in a very compact and fast gate circuit for Rijndael encryption. In conjunction with bit-slicing techniques applied to newly proposed par-allelizable modes of operation, our circuit leads to a high-performance software implementation for Rijndael encryption which offers significant speedup compared to previously reported implementations

Review of Graphene Technology and Its Applications for Electronic Devices

Graphene has amazing abilities due to its unique band structure characteristics defining its enhanced electrical capabilities for a material with the highest characteristic mobility known to exist at room temperature. The high mobility of graphene occurs due to electron delocalization and weak electron–phonon interaction, making graphene an ideal material for electrical applications requiring high mobility and fast response times. In this review, we cover graphene’s integration into infrared (IR) devices, electro-optic (EO) devices, and field effect transistors (FETs) for radio frequency (RF) applications. The benefits of utilizing graphene for each case are discussed, along with examples showing the current state-of-the-art solutions for these applications

Characterizing Vulnerability of Parallelism to Resource Constraints

The theoretical available instruction level parallelism in most benchmark is very high. Vulnerability is related to the difficulty with which we can extract this parallelism with finite resources. This study characterizes the vulnerability of parallelism to resource constraints by scheduling dynamic dependence graphs (DDGs) from traces of several benchmarks using different scheduling algorithms and different number of functional units. It is observed that the execution time of the DDGs does not vary significantly with low-level scheduling algorithms like lazy, slack, etc. Measures of vulnerability based on slack and load were also considered. Although Accslk-Load, which uses a combination of accurate slack and load to make a prediction, has a prediction accuracy of about 85%, the prediction rate is only 42%. On the other hand, even though the prediction accuracy of $\sigma(L_x)$, the standard deviation in the load, is not as high, there is a prediction in all the cases. The DDG execution time is also found to be most vulnerable to the functional unit with the greatest $\sigma(L_x)